\doxysection{DCMI\+\_\+\+Type\+Def Struct Reference}
\hypertarget{struct_d_c_m_i___type_def}{}\label{struct_d_c_m_i___type_def}\index{DCMI\_TypeDef@{DCMI\_TypeDef}}


DCMI.  




{\ttfamily \#include $<$stm32h723xx.\+h$>$}

\doxysubsubsection*{Public Attributes}
\begin{DoxyCompactItemize}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_d_c_m_i___type_def_a3cfcc9860ca551cbcb10c1c3dd4304f0}{CR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_d_c_m_i___type_def_a1bbe4b3cc5d9552526bec462b42164d5}{SR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_d_c_m_i___type_def_ae0aba9f38498cccbe0186b7813825026}{RISR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_d_c_m_i___type_def_a91ce93b57d8382147574c678ee497c63}{IER}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_d_c_m_i___type_def_ab367c4ca2e8ac87238692e6d55d622ec}{MISR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_d_c_m_i___type_def_a0371fc07916e3043e1151eaa97e172c9}{ICR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_d_c_m_i___type_def_a52c16b920a3f25fda961d0cd29749433}{ESCR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_d_c_m_i___type_def_af00a94620e33f4eff74430ff25c12b94}{ESUR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_d_c_m_i___type_def_a4d58830323e567117c12ae3feac613b9}{CWSTRTR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_d_c_m_i___type_def_a1b9c8048339e19b110ecfbea486f55df}{CWSIZER}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_d_c_m_i___type_def_a266cec1031b0be730b0e35523f5e2934}{DR}}
\end{DoxyCompactItemize}


\doxysubsection{Detailed Description}
DCMI. 

\label{doc-variable-members}
\Hypertarget{struct_d_c_m_i___type_def_doc-variable-members}
\doxysubsection{Member Data Documentation}
\Hypertarget{struct_d_c_m_i___type_def_a3cfcc9860ca551cbcb10c1c3dd4304f0}\index{DCMI\_TypeDef@{DCMI\_TypeDef}!CR@{CR}}
\index{CR@{CR}!DCMI\_TypeDef@{DCMI\_TypeDef}}
\doxysubsubsection{\texorpdfstring{CR}{CR}}
{\footnotesize\ttfamily \label{struct_d_c_m_i___type_def_a3cfcc9860ca551cbcb10c1c3dd4304f0} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t DCMI\+\_\+\+Type\+Def\+::\+CR}

DCMI control register 1, Address offset\+: 0x00 \Hypertarget{struct_d_c_m_i___type_def_a1b9c8048339e19b110ecfbea486f55df}\index{DCMI\_TypeDef@{DCMI\_TypeDef}!CWSIZER@{CWSIZER}}
\index{CWSIZER@{CWSIZER}!DCMI\_TypeDef@{DCMI\_TypeDef}}
\doxysubsubsection{\texorpdfstring{CWSIZER}{CWSIZER}}
{\footnotesize\ttfamily \label{struct_d_c_m_i___type_def_a1b9c8048339e19b110ecfbea486f55df} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t DCMI\+\_\+\+Type\+Def\+::\+CWSIZER}

DCMI crop window size, Address offset\+: 0x24 \Hypertarget{struct_d_c_m_i___type_def_a4d58830323e567117c12ae3feac613b9}\index{DCMI\_TypeDef@{DCMI\_TypeDef}!CWSTRTR@{CWSTRTR}}
\index{CWSTRTR@{CWSTRTR}!DCMI\_TypeDef@{DCMI\_TypeDef}}
\doxysubsubsection{\texorpdfstring{CWSTRTR}{CWSTRTR}}
{\footnotesize\ttfamily \label{struct_d_c_m_i___type_def_a4d58830323e567117c12ae3feac613b9} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t DCMI\+\_\+\+Type\+Def\+::\+CWSTRTR}

DCMI crop window start, Address offset\+: 0x20 \Hypertarget{struct_d_c_m_i___type_def_a266cec1031b0be730b0e35523f5e2934}\index{DCMI\_TypeDef@{DCMI\_TypeDef}!DR@{DR}}
\index{DR@{DR}!DCMI\_TypeDef@{DCMI\_TypeDef}}
\doxysubsubsection{\texorpdfstring{DR}{DR}}
{\footnotesize\ttfamily \label{struct_d_c_m_i___type_def_a266cec1031b0be730b0e35523f5e2934} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t DCMI\+\_\+\+Type\+Def\+::\+DR}

DCMI data register, Address offset\+: 0x28 \Hypertarget{struct_d_c_m_i___type_def_a52c16b920a3f25fda961d0cd29749433}\index{DCMI\_TypeDef@{DCMI\_TypeDef}!ESCR@{ESCR}}
\index{ESCR@{ESCR}!DCMI\_TypeDef@{DCMI\_TypeDef}}
\doxysubsubsection{\texorpdfstring{ESCR}{ESCR}}
{\footnotesize\ttfamily \label{struct_d_c_m_i___type_def_a52c16b920a3f25fda961d0cd29749433} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t DCMI\+\_\+\+Type\+Def\+::\+ESCR}

DCMI embedded synchronization code register, Address offset\+: 0x18 \Hypertarget{struct_d_c_m_i___type_def_af00a94620e33f4eff74430ff25c12b94}\index{DCMI\_TypeDef@{DCMI\_TypeDef}!ESUR@{ESUR}}
\index{ESUR@{ESUR}!DCMI\_TypeDef@{DCMI\_TypeDef}}
\doxysubsubsection{\texorpdfstring{ESUR}{ESUR}}
{\footnotesize\ttfamily \label{struct_d_c_m_i___type_def_af00a94620e33f4eff74430ff25c12b94} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t DCMI\+\_\+\+Type\+Def\+::\+ESUR}

DCMI embedded synchronization unmask register, Address offset\+: 0x1C \Hypertarget{struct_d_c_m_i___type_def_a0371fc07916e3043e1151eaa97e172c9}\index{DCMI\_TypeDef@{DCMI\_TypeDef}!ICR@{ICR}}
\index{ICR@{ICR}!DCMI\_TypeDef@{DCMI\_TypeDef}}
\doxysubsubsection{\texorpdfstring{ICR}{ICR}}
{\footnotesize\ttfamily \label{struct_d_c_m_i___type_def_a0371fc07916e3043e1151eaa97e172c9} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t DCMI\+\_\+\+Type\+Def\+::\+ICR}

DCMI interrupt clear register, Address offset\+: 0x14 \Hypertarget{struct_d_c_m_i___type_def_a91ce93b57d8382147574c678ee497c63}\index{DCMI\_TypeDef@{DCMI\_TypeDef}!IER@{IER}}
\index{IER@{IER}!DCMI\_TypeDef@{DCMI\_TypeDef}}
\doxysubsubsection{\texorpdfstring{IER}{IER}}
{\footnotesize\ttfamily \label{struct_d_c_m_i___type_def_a91ce93b57d8382147574c678ee497c63} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t DCMI\+\_\+\+Type\+Def\+::\+IER}

DCMI interrupt enable register, Address offset\+: 0x0C \Hypertarget{struct_d_c_m_i___type_def_ab367c4ca2e8ac87238692e6d55d622ec}\index{DCMI\_TypeDef@{DCMI\_TypeDef}!MISR@{MISR}}
\index{MISR@{MISR}!DCMI\_TypeDef@{DCMI\_TypeDef}}
\doxysubsubsection{\texorpdfstring{MISR}{MISR}}
{\footnotesize\ttfamily \label{struct_d_c_m_i___type_def_ab367c4ca2e8ac87238692e6d55d622ec} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t DCMI\+\_\+\+Type\+Def\+::\+MISR}

DCMI masked interrupt status register, Address offset\+: 0x10 \Hypertarget{struct_d_c_m_i___type_def_ae0aba9f38498cccbe0186b7813825026}\index{DCMI\_TypeDef@{DCMI\_TypeDef}!RISR@{RISR}}
\index{RISR@{RISR}!DCMI\_TypeDef@{DCMI\_TypeDef}}
\doxysubsubsection{\texorpdfstring{RISR}{RISR}}
{\footnotesize\ttfamily \label{struct_d_c_m_i___type_def_ae0aba9f38498cccbe0186b7813825026} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t DCMI\+\_\+\+Type\+Def\+::\+RISR}

DCMI raw interrupt status register, Address offset\+: 0x08 \Hypertarget{struct_d_c_m_i___type_def_a1bbe4b3cc5d9552526bec462b42164d5}\index{DCMI\_TypeDef@{DCMI\_TypeDef}!SR@{SR}}
\index{SR@{SR}!DCMI\_TypeDef@{DCMI\_TypeDef}}
\doxysubsubsection{\texorpdfstring{SR}{SR}}
{\footnotesize\ttfamily \label{struct_d_c_m_i___type_def_a1bbe4b3cc5d9552526bec462b42164d5} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t DCMI\+\_\+\+Type\+Def\+::\+SR}

DCMI status register, Address offset\+: 0x04 

The documentation for this struct was generated from the following file\+:\begin{DoxyCompactItemize}
\item 
C\+:/\+Users/\+ASUS/\+Desktop/dm-\/ctrl\+H7-\/balance-\/9025test/\+Drivers/\+CMSIS/\+Device/\+ST/\+STM32\+H7xx/\+Include/\mbox{\hyperlink{stm32h723xx_8h}{stm32h723xx.\+h}}\end{DoxyCompactItemize}
